IC PACKAGING ENGINEER
Teradar
San Francisco, CA, USA · Boston, MA, USA
Posted on Jan 30, 2026
Responsibilities- Provide technical leadership for advanced IC packages for multi‑chip RFIC/SoC integration.- Develop 2.5D packages with UCIe interconnects and interposer‑based solutions.- Work on single‑/double‑sided RDL and on‑package RF antenna structures.- Co‑optimize for SI/PI, thermal, and mechanical performance with RFIC, digital, and system engineers.- Drive material selection, DFM, and reliability qualification to meet automotive‑grade requirements (AEC‑Q).- Perform stress, warpage, and thermal simulations (e.g., ANSYS).- Maintain relationships with OSATs, substrate suppliers, and partners.- Create/review electrical performance analyses, mechanical analyses, drawings, stack‑ups, layout constraints.- Lead failure analysis/root cause for packaging/reliability issues; improve yield.- Contribute to packaging roadmap and scalability for automotive volume production. Key Qualifications- 10+ years in IC packaging design/development with leadership.- Proven track record with multi‑chip packages, digital + RF integration, automotive.- Deep knowledge of UCIe, organic substrates, interposers, advanced packaging architectures.- Experience with RF antenna integration in packages.- Proficient in Flip‑Chip, Fan‑Out, 2.5D, heterogeneous SiP.- Strong understanding of SI/PI, mechanical stress, thermal management, reliability.- Established vendor/OSAT network.- M.S./Ph.D. in ME, MSE, EE, or related.- Excellent communication; thrive in fast‑paced start‑up. Why Join- Technical oversight defining packaging for breakthrough ADAS.- Collaborate with world‑class team across RFIC, SoC, and system design.- Be part of a well‑funded start‑up bringing innovative sensing tech to market.- Competitive compensation, stock options, flexible work. LocationHybrid from one of our offices: Bay Area, CA; Boston, MA.