About Teradar Teradar is building sub-terahertz imaging radar for automotive perception. Our sensor architecture combines millimeter-wave transmit and receive front-ends, a high-channel-count data conversion front-end, and an integrated radar signal processor. These are automotive parts headed for AEC-Q qualification and volume production with Tier 1 customers. The Role Our next-generation sensor SoC is a multi-chip module that co-packages a high-channel-count mixed-signal data conversion die with a digital compute die carrying a real-time processor, DSP cluster with FFT acceleration, GPU, functional safety monitor, hardware security module, external DRAM interface, and automotive Ethernet. The two dies communicate over a high-speed die-to-die link across a fine-pitch, automotive-grade interposer. We are looking for the engineer who will own the product test for this module. You will define and drive wafer probe and final test for both dies and for the integrated package — building the test programs, owning the test hardware, and managing our contract manufacturers, OSATs, and test houses to get from first silicon to qualified, yielding, production-tested parts. Responsibilities include first-silicon bring-up, wafer probe (sort), final test and ATE program development, working with contract manufacturers and test partners, AEC-Q qualification, and production yield/test optimization. Requirements: BS/MS in Electrical Engineering or equivalent with 8–15 years in product or test engineering for production silicon; ownership from first silicon through production; experience on production ATE platforms; both analog/mixed-signal and digital test experience; strong wafer probe background; experience managing OSATs/test houses; AEC-Q100 qualification experience; load/char board design; fluency in test data analysis and statistics. Strongly preferred: AEC-Q104 or multi-chip module qualification, chiplet/die-to-die test, high-speed interface test, automotive functional safety context, radar/data converter/RF test background, burn-in/HTOL, startup test capability setup.