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Design Verification Engineer to Staff Engineer (Unit Level Test)
Design Verification Engineer to Staff Engineer (Unit Level Test)
Location: Hsinchu City, Taiwan 300
Posted:
6+ months
Mid-Senior Level
Application Specific Integrated Circuit (ASIC)
Computer
Electronics
Embedded Systems
Field-Programmable Gate Array (FPGA)
Hardware
Industrial Manufacturing
Intellectual Property
Manufacturing
RISC
Semiconductor
Software
Mid-Senior Level
Application Specific Integrated Circuit (ASIC)
Computer
Electronics
Embedded Systems
Field-Programmable Gate Array (FPGA)
Hardware
Industrial Manufacturing
Intellectual Property
Manufacturing
RISC
Semiconductor
Software
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